A. Field of the Invention
This invention relates generally to a system for detecting malfunction of a binary counter, and more particularly to an error detection system utilizing the parity of the prior count, the parity of the current count, and the predicted parity of the next sequential count to determine whether the counter has failed to change to the next numerical state upon application of the count advance signal.
B. Description of the Prior Art
Parity system are well-known in the prior art to provide a means for determining whether an operand has been calculate or transferred accurately. In binary systems, it is common to utilize circuitry that will determine whether the number of one's in the binary operand is an odd or even count. A parity bit is then associated with the operand and is set to the one or zero state depending upon whether an odd or even parity system is used, such that the number one bits in the operand together with the parity bit constitutes an odd count for odd parity, or an even count for even parity. For example, if there is a three-bit operand of the binary bits 011, and an odd parity system is utilized, it can be seen that the parity bit must be a binary one in order for the total count of binary one's in the operand plus the parity bit to be an odd count. For the same example, if the system was to be an even parity, the parity bit would be 0 since there would be two (even) binary one's in the operand.
Various prior art teachings relate to the theories and techniques of utilization of various parity systems. Many prior art teachings recognize the desirability of predicting the resultant parity bit that will be required for operands in transition during calculation processes. One such recognition of various forms of parity prediction is set forth in a treatise entitled "Fault-Tolerant Computing: Theory and Techniques", in Volume I, at section 5.2.3 commencing at page 344 and running through page 359, entitled "Parity Prediction", Dhiraj K. Pradhan, Editor, available from Prentice-Hall. While this treatise illustrates various forms of the use of parity prediction in use in various calculations and operation of adders and multipliers, it does not teach a system for use of parity bits for sequential counts to test that a binary counter accurately changes its count state for each occurrence of an count pulse.
In U.S. Pat. No. 4,291,407, entitled PARITY PREDICTION CIRCUITRY FOR A MULTIFUNCTION REGISTER, to Roffe D. Armstrong, it is recognized that it is desirable to check parity when data words are passed through registers, especially where the data words may be altered depending upon control signals applied to such registers. Armstrong describes a parity prediction circuit associated with each function of the particular register and to be utilized for predicting the parity of the data word ultimately to be stored in the register following the functional operation of the register. One of the operations involving a multifunction register it is described to be a counting function such as used in an incrementing binary counter. Armstrong describes complex circuitry involving several multiplexers and functions to respond to existing parity bits to predict future parity and determine accuracy of the function. Armstrong does not, however, teach the use of multiple sequential parity signals to assure that a counter that sticks in operation and does not advance in count with sequential advance count signals will be detected during the advance count cycle during which the counter operations sticks.
U.S. Pat. No. 3,567,916, entitled APPARATUS FOR PARITY CHECKING A BINARY REGISTER issued to James M. Fullton, Jr., et at., recognizes that in a binary counter the parity bits will change for advancing counts in a predictable fashion. Fullton, Jr., et at. describes an error checking system for use with a binary counter wherein the parity of the current count is compared to a previously stored predicted parity for determining that the circuit has properly advanced. This configuration, utilizes a set and reset tip-flop for recording the predicted parity during the previous count cycle. The Fullton, Jr., et at. system is deficient in that it appears that a stuck counter may not be detected immediately. Further, it appears that if the counter sticks at the most in opportune time it may not detect the stuck counter. In the best case, the Fullton, Jr., et at. device may allow at least two sequences of erroneous count before the predicted count will appropriately change to signal the error condition. This operation will allow the operation and the data involved to be corrupted.
From the foregoing, it can be seen that all of the prior art teachings have been limited to use of the parity bit for the operand word under consideration and a predicted parity based upon a formulation and system for predicting the parity outcome. None of them recognize that when applied to sequential counts, that the two parity bits are insufficient to immediately detect a stuck counter. The occurrence of multiple cycles of a stuck counter can cause serious problems of corrupted operation or corrupted data.